1. Field of the Invention
The present invention relates to shift register circuits used in display apparatuses and image sensors, and more particularly, to a shift register circuit which sends a clock signal to a shift register.
2. Description of the Related Art
FIG. 19 is a circuit diagram of a conventional shift register circuit. The shift register circuit includes a first shift register in which a plurality of stages F′1, F′2, F′3, . . . , and F′m are connected in cascade, and a second shift register in which a plurality of stages F1, F2, F3, . . . , and Fn are connected in cascade and three consecutive stages form one group. In the second shift register, for example, stages F1, F2, and F3 form one group Gr1.
Three-phase clock signals φa, φb, and φc are input to the second shift register through gate circuits Ge1, Ge2, Ge3, . . . , and Gem. These clock signals φa, φb, and φc are selectively sent to the groups of the second shift register when the outputs S1, S2, S3, . . . , and Sm of the first shift register are input to the gate circuits Ge1, Ge2, Ge3, . . . , and Gem. Such selective clock-signal inputs are used for reducing the power consumption of the shift register circuit. The outputs G1, G2, G3, . . . , and Gn of the second shift register drive a display apparatus or the like.
FIG. 20 is a timing chart showing the operation of the shift register circuit. When a start pulse SP′ is input to a first stage F′1 of the first shift register, the pulse is sequentially passed to the following stages. The signal S1 is first output, then the signal S2, and the signals S3, S4, . . . , and Sm are sequentially output. These signals S1, S2, S3, . . . , and Sm are input to the gate circuits Ge1, Ge2, Ge3, . . . , and Gem, respectively, and these gate circuits Ge1, Ge2, GE3, . . . , and Gem select necessary pulses among the pulse sequences of the three-phase clock signals φa, 100 b, and φc according to the signals S1, S2, S3, . . . , and Sm. For example, the gate circuit Ge1 selects clock signals φ1a, φ2b, and φ1c, and the gate circuit Ge2 selects clock signals φ2a, φ2b, and φ2c. 
Clock signals selected by the gate circuits Ge1, Ge2, Ge3, . . . , and Gem are sent to the groups of the second shift register. The clock signals φ1a, φ1b, and φc selected by the gate circuit Ge1, for example, are sent to the group Gr1, and input to the stages F1, F2, and F3 of the group Gr1. At the same time, the start pulse SP is input to the first stage F1 of the second shift register. The stages F1, F2, and F3 of the second shift register sequentially output signals G1, G2, and G3, and stages F4 and subsequent stages sequentially output signals G4, G5, G6, . . . , and Gn in the same way.
The above-described conventional technology has the following problem. In the conventional technology, the outputs S1, S2, S2, . . . , and Sm of the first shift register are sent to the gate circuits Ge1, Ge2, Ge3, . . . , and Gem, and the gate circuits Ge1, Ge2, Ge3, . . . , and Gem select the clock signals φa, φb, and φc for the groups of the second shift register. Therefore, the gate circuits Ge1, Ge2, Ge3, . . . , and Gem need to be disposed between the first shift register and the second shift register, and thereby, the shift register circuit has a large circuit scale.
To form the gate circuits Ge1, Ge2, Ge3, . . . , and Gem and the second register on the same substrate (glass substrate) as a display apparatus, transistors in these gate circuits and the second shift register need to be made from a material such as amorphous silicon or polycrystalline silicon. When voltages are continually applied to transistors made from these materials, the characteristics of the transistors deteriorate due to voltage stress and their reliability is reduced in some cases. Therefore, it is important that voltage is applied to such transistors as little as possible. In the above conventional technology, since the gate circuits Ge1, Ge2, Ge3, . . . , and Gem are always operating, voltages are always applied to transistors in these gate circuits, leading to the reduced reliability of the transistors due to the stress of the voltages.